blog about Imx6 Processors Enable Highresolution Displays Beyond Singlechannel LVDS Limits

In embedded system design, driving high-resolution, high-refresh-rate LVDS displays has become an increasingly common yet challenging task. Particularly when targeting a display that supports only a single-channel LVDS interface with a resolution of 1920x1080@60Hz, the required pixel clock (Dotclock) of 148.5 MHz imposes significant demands on the interface controller's data transmission rate. This article delves into the core technical bottlenecks encountered during such interface adaptations and explores solutions based on the i.MX6 series of processors, aiming to provide engineers with clear guidance and practical technical insights.

Technical Bottleneck: Rate Limitations of Single-Channel LVDS

For a display with a resolution of 1920x1080@60Hz, the pixel clock (Dotclock) is 148.5 MHz. LVDS (Low-Voltage Differential Signaling) interfaces transmit data via differential signals to reduce electromagnetic interference and improve transmission rates. In a single-channel LVDS configuration, each pair of differential lines typically transmits one data bit. To calculate the required serializer clock, the effective number of data bits must be considered. A common LVDS data transmission model maps 8-bit pixel data (RGB channels) to the data lines. However, the actual LVDS transmission rate is not a simple multiple of the pixel clock; it involves factors such as data encoding and clock multiplication.

The calculation of "148.5 MHz Dotclock * 7 Databit = 1039.5 MHz Serializer Clock" may deviate from standard practices or rely on a specific encoding scheme. A more conventional understanding is that the serializer clock for single-channel LVDS transmission of a 1920x1080@60Hz video signal is typically a multiple of the pixel clock to cover all pixel data and synchronization signals. For example, if 8-bit pixel data transmission is used, the serializer clock theoretically needs to be 8 times the pixel clock. However, actual LVDS interface designs and data mapping methods may vary. The core issue is that if the maximum serializer clock frequency of a single-channel LVDS interface is limited (e.g., 595 MHz as mentioned), directly using single-channel transmission for high-resolution signals will exceed its capabilities.

Conclusion: The proposed "1039.5 MHz Serializer Clock" likely exceeds the hardware limitations of many single-channel LVDS interfaces (e.g., 595 MHz), making it infeasible to drive a 1920x1080@60Hz display directly with a single-channel LVDS interface.

Solution: Dual-Channel LVDS Mode in i.MX6 Processors

To address the rate limitations of single-channel LVDS, a common solution is to leverage the dual-channel LVDS output capability of processors like the i.MX6 series. Dual-channel LVDS mode splits the data stream into two independent LVDS channels, effectively halving the total data rate and reducing the serializer clock requirement for each channel.

In this mode, data is divided into odd (ODD) and even (EVEN) parts, transmitted through two LVDS channels. If the original serializer clock requirement was 1039.5 MHz, dual-channel mode reduces it to approximately 519.75 MHz per channel, which typically falls within the i.MX6 processor's LVDS interface capabilities (e.g., below the 595 MHz limit).

Conclusion: Using the i.MX6's dual-channel LVDS mode (SPLIT mode) is an effective solution to reduce serializer clock requirements. However, this requires the display itself to support dual-channel LVDS input, meaning it must correctly merge data streams from both channels.

Key Information: Identifying ODD/EVEN Data Channels

When using dual-channel LVDS mode, a critical question is determining which LVDS channel (typically a physical interface on the PHY) transmits ODD data and which transmits EVEN data. This directly affects display driver configuration and physical signal connections.

Information about ODD/EVEN data channel allocation can typically be found in the following sources:

1. i.MX6 Technical Reference Manual (TRM): The most authoritative source, detailing LVDS controller operation, register configuration, and channel mapping. The TRM usually specifies which physical output ports (e.g., LVDS0_TXP/N, LVDS1_TXP/N) correspond to odd or even data streams.
2. i.MX6 Electrical Characteristics or Datasheet: These documents provide pin definitions and functional descriptions, which may indirectly indicate channel allocation.
3. Official EVK Development Board Schematics: If using an i.MX6 development board, its schematics clearly show LVDS interface connections and how the processor's LVDS output pins link to transceivers or display interfaces.
4. Display Datasheet or User Manual: While primary information resides on the processor side, the display's documentation may provide LVDS interface pin definitions, including support for dual-channel mode and expected data channel order.
5. LVDS Driver/PHY Chip Datasheet: If an independent LVDS driver or PHY chip (e.g., TI's SN65LVDS series) is used, its datasheet will contain critical information about channel configuration and signal allocation.

Note: Always consult the latest technical documents for the specific i.MX6 model (e.g., i.MX6Solo, i.MX6Dual, i.MX6Quad) as interface configurations may vary. Communication with display manufacturers for LVDS interface requirements is also crucial for successful adaptation.

Summary

Adapting a single-channel LVDS display with a resolution of 1920x1080@60Hz faces hardware limitations due to data rate constraints. The i.MX6 series processors offer a viable solution through dual-channel LVDS output, splitting the data stream to reduce serializer clock requirements per channel. The most reliable source for ODD/EVEN data channel allocation is the i.MX6 Technical Reference Manual (TRM), supplemented by datasheets, development board schematics, and display/PHY chip documentation. Careful study of these materials and proper software configuration are key to achieving high-resolution LVDS display functionality.